This invention relates to a multiprocessor system in general and, more particularly to a bus window interlock scheme for a multiprocessor system.
The use of a single bus in a multiprocessor system presents several difficulties. In order to accomodate several nodes on a bus, the electrical loading of the bus is significantly increased. This slows down the cycle time of the system. Further, the arbitration time is increased as all of the nodes must wait for a single bus. Also, the use of only one bus presents heavy traffic problems and unnecessary congestion.
One solution to the above problems is the use of two separate busses interconnected through a bus window. This serves to virtually extend the bus to accomodate several nodes while not actually increasing the electrical loading on the bus. Further, it allows the extension of the bus beyond a single cabinet.
However, a difficulty arises with interlock transactions which must be passed through the bus window. When a processor generates an interlock read command to access memory, it must be sent through the bus window. If accepted by the memory, the interlock read command will lock the memory until an unlock write signal is generated. If the memory is already locked, then the interlock read command is stored in a buffer until an unlock write signal from the processor unlocks the memory. Deadlock situations present themselves where the memory is locked, an interlock read is waiting in the buffer and an unlock write signal is behind the interlock read in the same buffer.